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• R

  Senior Memory Design Engineer  

  Rivos

  full_time - Austin

  Posted: 17/10/2025

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  Job DescriptionJob DescriptionRivos Custom Circuits team is seeking hi... Read More

  Job DescriptionJob DescriptionRivos Custom Circuits team is seeking highly motivated candidates to develop state of the art custom SRAM memories, Register file memories, and compiled memories  to improve circuit performance, optimize dynamic and static power and support silicon bring up. The role will be at the center of a state-of-the art circuit design effort, interfacing with all disciplines and have a critical impact on getting products to market quickly.  The qualified candidate will be responsible for designing and delivering custom circuits from scratch.  Candidates must have 8-10 years of experience in transistor level circuit design, circuit simulation, equivalence checking,  PPA trade off analysis, low power design techniques, timing, noise and power characterization. Key QualificationsThe ideal candidate will have 12-15 years of custom circuit design experience from RTL-GDS for CPU and SoC applicationsPrior experience and proven success of successfully designing high performance SRAM memories, Register file memories, SRAM compilers, data path designs and standard cellsExperience designing transistor-level custom circuits in advanced FinFET technology nodesMust have a solid experience with the custom circuit tool flows for delivering design collateralsA solid understanding of device physics, process technology and circuit design techniques for high performance, low power, and power gatingExperience with advanced process design rules and supervising mask designKnowledge developing automation for compilers and standard cellsPost-Silicon test and debug experienceAbility to work well in a team and be productive under aggressive schedules.Excellent problem solving, written and verbal communicationResponsibilitiesDrive design and development of SRAM, register file, custom cells to enable high performance and low power designsWork with microarchitecture team to gather specifications and drive optimal implementation Conduct early sizing estimates and PPA analysis . Design entry and simulations for optimal design sizing.Design equivalence checking using the latest industry standard LEC toolsWork closely with mask designers on custom design implementation, DFM and  yield enhancement featuresDeliver high quality design collateral Collaborate with the CPU and SoC Physical design teams on floorplanning, placement, timing and power closure of the custom designInteract with technology team, participate in developing design and test plans Collaborate with CAD teams and drive design flow enhancementsEducation and ExperienceMaster’s Degree or Bachelor’s Degree with  12-15 years of experience

  We may use artificial intelligence (AI) tools to support parts of the hiring process, such as reviewing applications, analyzing resumes, or assessing responses. These tools assist our recruitment team but do not replace human judgment. Final hiring decisions are ultimately made by humans. If you would like more information about how your data is processed, please contact us.

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• R

  Senior Memory Design Engineer  

  Rivos

  full_time - Santa Clara

  Posted: 17/10/2025

  Apply Now

  Job DescriptionJob DescriptionRivos Custom Circuits team is seeking hi... Read More

  Job DescriptionJob DescriptionRivos Custom Circuits team is seeking highly motivated candidates to develop state of the art custom SRAM memories, Register file memories, and compiled memories  to improve circuit performance, optimize dynamic and static power and support silicon bring up. The role will be at the center of a state-of-the art circuit design effort, interfacing with all disciplines and have a critical impact on getting products to market quickly.  The qualified candidate will be responsible for designing and delivering custom circuits from scratch.  Candidates must have 8-10 years of experience in transistor level circuit design, circuit simulation, equivalence checking,  PPA trade off analysis, low power design techniques, timing, noise and power characterization. Key QualificationsThe ideal candidate will have 12-15 years of custom circuit design experience from RTL-GDS for CPU and SoC applicationsPrior experience and proven success of successfully designing high performance SRAM memories, Register file memories, SRAM compilers, data path designs and standard cellsExperience designing transistor-level custom circuits in advanced FinFET technology nodesMust have a solid experience with the custom circuit tool flows for delivering design collateralsA solid understanding of device physics, process technology and circuit design techniques for high performance, low power, and power gatingExperience with advanced process design rules and supervising mask designKnowledge developing automation for compilers and standard cellsPost-Silicon test and debug experienceAbility to work well in a team and be productive under aggressive schedules.Excellent problem solving, written and verbal communicationResponsibilitiesDrive design and development of SRAM, register file, custom cells to enable high performance and low power designsWork with microarchitecture team to gather specifications and drive optimal implementation Conduct early sizing estimates and PPA analysis . Design entry and simulations for optimal design sizing.Design equivalence checking using the latest industry standard LEC toolsWork closely with mask designers on custom design implementation, DFM and  yield enhancement featuresDeliver high quality design collateral Collaborate with the CPU and SoC Physical design teams on floorplanning, placement, timing and power closure of the custom designInteract with technology team, participate in developing design and test plans Collaborate with CAD teams and drive design flow enhancementsEducation and ExperienceMaster’s Degree or Bachelor’s Degree with  12-15 years of experience

  We may use artificial intelligence (AI) tools to support parts of the hiring process, such as reviewing applications, analyzing resumes, or assessing responses. These tools assist our recruitment team but do not replace human judgment. Final hiring decisions are ultimately made by humans. If you would like more information about how your data is processed, please contact us.

  Read Less

  Apply Now
• R

  Senior Memory Design Engineer  

  Rivos

  full_time - Austin

  Posted: 17/10/2025

  Apply Now

  Job DescriptionJob DescriptionRivos Custom Circuits team is seeking hi... Read More

  Job DescriptionJob DescriptionRivos Custom Circuits team is seeking highly motivated candidates to develop state of the art custom SRAM memories, Register file memories, and compiled memories  to improve circuit performance, optimize dynamic and static power and support silicon bring up. The role will be at the center of a state-of-the art circuit design effort, interfacing with all disciplines and have a critical impact on getting products to market quickly.  The qualified candidate will be responsible for designing and delivering custom circuits from scratch.  Candidates must have 8-10 years of experience in transistor level circuit design, circuit simulation, equivalence checking,  PPA trade off analysis, low power design techniques, timing, noise and power characterization. Key QualificationsThe ideal candidate will have 12-15 years of custom circuit design experience from RTL-GDS for CPU and SoC applicationsPrior experience and proven success of successfully designing high performance SRAM memories, Register file memories, SRAM compilers, data path designs and standard cellsExperience designing transistor-level custom circuits in advanced FinFET technology nodesMust have a solid experience with the custom circuit tool flows for delivering design collateralsA solid understanding of device physics, process technology and circuit design techniques for high performance, low power, and power gatingExperience with advanced process design rules and supervising mask designKnowledge developing automation for compilers and standard cellsPost-Silicon test and debug experienceAbility to work well in a team and be productive under aggressive schedules.Excellent problem solving, written and verbal communicationResponsibilitiesDrive design and development of SRAM, register file, custom cells to enable high performance and low power designsWork with microarchitecture team to gather specifications and drive optimal implementation Conduct early sizing estimates and PPA analysis . Design entry and simulations for optimal design sizing.Design equivalence checking using the latest industry standard LEC toolsWork closely with mask designers on custom design implementation, DFM and  yield enhancement featuresDeliver high quality design collateral Collaborate with the CPU and SoC Physical design teams on floorplanning, placement, timing and power closure of the custom designInteract with technology team, participate in developing design and test plans Collaborate with CAD teams and drive design flow enhancementsEducation and ExperienceMaster’s Degree or Bachelor’s Degree with  12-15 years of experience

  We may use artificial intelligence (AI) tools to support parts of the hiring process, such as reviewing applications, analyzing resumes, or assessing responses. These tools assist our recruitment team but do not replace human judgment. Final hiring decisions are ultimately made by humans. If you would like more information about how your data is processed, please contact us.

  Read Less

  Apply Now
• R

  Senior Memory Design Engineer  

  Rivos

  full_time - Portland

  Posted: 17/10/2025

  Apply Now

  Job DescriptionJob DescriptionRivos Custom Circuits team is seeking hi... Read More

  Job DescriptionJob DescriptionRivos Custom Circuits team is seeking highly motivated candidates to develop state of the art custom SRAM memories, Register file memories, and compiled memories  to improve circuit performance, optimize dynamic and static power and support silicon bring up. The role will be at the center of a state-of-the art circuit design effort, interfacing with all disciplines and have a critical impact on getting products to market quickly.  The qualified candidate will be responsible for designing and delivering custom circuits from scratch.  Candidates must have 8-10 years of experience in transistor level circuit design, circuit simulation, equivalence checking,  PPA trade off analysis, low power design techniques, timing, noise and power characterization. Key QualificationsThe ideal candidate will have 12-15 years of custom circuit design experience from RTL-GDS for CPU and SoC applicationsPrior experience and proven success of successfully designing high performance SRAM memories, Register file memories, SRAM compilers, data path designs and standard cellsExperience designing transistor-level custom circuits in advanced FinFET technology nodesMust have a solid experience with the custom circuit tool flows for delivering design collateralsA solid understanding of device physics, process technology and circuit design techniques for high performance, low power, and power gatingExperience with advanced process design rules and supervising mask designKnowledge developing automation for compilers and standard cellsPost-Silicon test and debug experienceAbility to work well in a team and be productive under aggressive schedules.Excellent problem solving, written and verbal communicationResponsibilitiesDrive design and development of SRAM, register file, custom cells to enable high performance and low power designsWork with microarchitecture team to gather specifications and drive optimal implementation Conduct early sizing estimates and PPA analysis . Design entry and simulations for optimal design sizing.Design equivalence checking using the latest industry standard LEC toolsWork closely with mask designers on custom design implementation, DFM and  yield enhancement featuresDeliver high quality design collateral Collaborate with the CPU and SoC Physical design teams on floorplanning, placement, timing and power closure of the custom designInteract with technology team, participate in developing design and test plans Collaborate with CAD teams and drive design flow enhancementsEducation and ExperienceMaster’s Degree or Bachelor’s Degree with  12-15 years of experience

  We may use artificial intelligence (AI) tools to support parts of the hiring process, such as reviewing applications, analyzing resumes, or assessing responses. These tools assist our recruitment team but do not replace human judgment. Final hiring decisions are ultimately made by humans. If you would like more information about how your data is processed, please contact us.

  Read Less

  Apply Now
• R

  Senior Memory Design Engineer  

  Rivos

  full_time - Fort Collins

  Posted: 17/10/2025

  Apply Now

  Job DescriptionJob DescriptionRivos Custom Circuits team is seeking hi... Read More

  Job DescriptionJob DescriptionRivos Custom Circuits team is seeking highly motivated candidates to develop state of the art custom SRAM memories, Register file memories, and compiled memories  to improve circuit performance, optimize dynamic and static power and support silicon bring up. The role will be at the center of a state-of-the art circuit design effort, interfacing with all disciplines and have a critical impact on getting products to market quickly.  The qualified candidate will be responsible for designing and delivering custom circuits from scratch.  Candidates must have 8-10 years of experience in transistor level circuit design, circuit simulation, equivalence checking,  PPA trade off analysis, low power design techniques, timing, noise and power characterization. Key QualificationsThe ideal candidate will have 12-15 years of custom circuit design experience from RTL-GDS for CPU and SoC applicationsPrior experience and proven success of successfully designing high performance SRAM memories, Register file memories, SRAM compilers, data path designs and standard cellsExperience designing transistor-level custom circuits in advanced FinFET technology nodesMust have a solid experience with the custom circuit tool flows for delivering design collateralsA solid understanding of device physics, process technology and circuit design techniques for high performance, low power, and power gatingExperience with advanced process design rules and supervising mask designKnowledge developing automation for compilers and standard cellsPost-Silicon test and debug experienceAbility to work well in a team and be productive under aggressive schedules.Excellent problem solving, written and verbal communicationResponsibilitiesDrive design and development of SRAM, register file, custom cells to enable high performance and low power designsWork with microarchitecture team to gather specifications and drive optimal implementation Conduct early sizing estimates and PPA analysis . Design entry and simulations for optimal design sizing.Design equivalence checking using the latest industry standard LEC toolsWork closely with mask designers on custom design implementation, DFM and  yield enhancement featuresDeliver high quality design collateral Collaborate with the CPU and SoC Physical design teams on floorplanning, placement, timing and power closure of the custom designInteract with technology team, participate in developing design and test plans Collaborate with CAD teams and drive design flow enhancementsEducation and ExperienceMaster’s Degree or Bachelor’s Degree with  12-15 years of experience

  We may use artificial intelligence (AI) tools to support parts of the hiring process, such as reviewing applications, analyzing resumes, or assessing responses. These tools assist our recruitment team but do not replace human judgment. Final hiring decisions are ultimately made by humans. If you would like more information about how your data is processed, please contact us.

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• R

  Software Compiler - Full Time  

  Rivos

  full_time - Remote

  Posted: 17/10/2025

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  Job DescriptionJob DescriptionWe are working on software to improve th... Read More

  Job DescriptionJob DescriptionWe are working on software to improve the RISC-V ecosystem and help hardware engineers build great RISC-V based systems.
  Compilers and related parts of the toolchain (assembler, linker, loader, etc) are key tools in connecting software with the hardware it runs on. We are building a world-class team to deliver the next generation of static and dynamic compilation and optimization software as open source.
  You will be learning technical and organizational skills from industry veterans: how to write performant and readable code; how to structure and communicate projects, ideas, and progress; how to work effectively with the Open Source community.
  We are big proponents of Open Source and Free software and contribute back our improvements to all the great projects we use.ResponsibilitiesAdding new features to LLVM, GCC, binutils, or other open-source projects.Collaborating cross-functionally with Silicon design, architecture experts, and other teams across the company.Running benchmarks or key customer workloads under simulation to identify performance bottlenecks.RequirementsC or C++ experience requiredRust experience is not necessary, but a plus.Knowledge of LLVM or GCC internals required.Excellent skills in problem solving, written and verbal communication, excellent organization skills, and highly self-motivated.Ability to work well in a team and be productive under aggressive schedules.Education and ExperiencePhD, Master’s Degree or Bachelor’s Degree in technical subject area.

  We may use artificial intelligence (AI) tools to support parts of the hiring process, such as reviewing applications, analyzing resumes, or assessing responses. These tools assist our recruitment team but do not replace human judgment. Final hiring decisions are ultimately made by humans. If you would like more information about how your data is processed, please contact us.

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• R

  Floating Point Logic Design  

  Rivos

  full_time - Austin

  Posted: 17/10/2025

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  Job DescriptionJob DescriptionFull-time positions are open in the area... Read More

  Job DescriptionJob DescriptionFull-time positions are open in the areas of floating point and logic design.ResponsibilitiesAs a Floating Point & Logic Design Engineer, you will own or participate in the following: Microarchitecture development and specification - from early high-level architectural exploration through micro architectural research and arriving at a detailed specificationDevelopment, assessment, and refinement of RTL design to target power, performance, area, and timing goalsDesign delivery - work with multi-functional engineering team to implement and validate physical design on the aspects of timing, area, reliability, testability and powerValidation - support test bench development and simulation for functional and performance verificationPerformance exploration and correlation - explore high performance strategies and validate that the RTL design meets targeted performanceRequirementsThorough knowledge of CPU or AI accelerator design work experience in one or more of the following areas:In-depth knowledge of IEEE-754, and experience in optimizing FMA operations.Creativity in designing various implementation methods to balance performance, power, and area when dealing with both integer and floating point operations for high performance, energy efficient components.Expertise in coding complex mathematical functions (such as logarithms, exponentials, etc.) at a very fine level of precision using C or other high-level programming languages.Working knowledge of Hector, c2rtl, or similar tools used for formal verification.Understanding the algorithms used in common ALUs like multipliers and the tradeoff between area and power.Knowledge of System VerilogExperience with simulators and waveform debugging toolsKnowledge of logic design principles along with timing and power implicationsUnderstanding of low power microarchitecture techniquesUnderstanding of high performance techniques and trade-offs in a CPU microarchitectureExperience in C or C++ programmingEducation and ExperiencePhD, Master’s Degree or Bachelor’s Degree in technical subject area.

  We may use artificial intelligence (AI) tools to support parts of the hiring process, such as reviewing applications, analyzing resumes, or assessing responses. These tools assist our recruitment team but do not replace human judgment. Final hiring decisions are ultimately made by humans. If you would like more information about how your data is processed, please contact us.

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• R

  SoC Fabric Architect  

  Rivos

  full_time - Santa Clara

  Posted: 16/10/2025

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  Job DescriptionJob DescriptionJoin Rivos Inc., a well-funded exciting... Read More

  Job DescriptionJob DescriptionJoin Rivos Inc., a well-funded exciting start-up whose mission is to create industry transforming RISC-V based and accelerated computing platforms with HW/SW co-design.  We offer a creative, flexible, and fun-filled environment where your work and innovation is prized and contributes to our mission. ResponsibilitiesYou will be working closely with architects, micro-architects, and software, performance, validation, and physical design teams to own or actively participate in: Architectural definition and specification of fabrics:Inter- and intra-chip interconnectsCoherent, non-coherent, and bridging protocolsWorking with SoC architects to optimize fabrics for overall system architectureDeveloping, assessing, and refining fabric architectures with appropriate trade-off analysis to target power, performance, area, and timing goalsHelping produce and review validation plans for functionality and performanceRequirementsKnowledge of SoC architectures including caching hierarchy and memory subsystems, with relevant experience Understanding of on-chip and off-chip topologies and interconnects with experience in architecture and design relevant subsystemsKnowledge of and experience with cache-coherent and non-coherent protocols (e.g., directory based implementations to resolve conflicts, deadlocks, etc.)Experience with functional and performance simulators: design space exploration, modeling and analysis, knowledge of toolsRelevant design experience exemplifying architectural/performance/power trade-offs.Education and ExperiencePh.D.: 3-5 years experience, orMaster’s: 5-7 years industry experience, orBachelor’s: 7-10 years industry experience

  We may use artificial intelligence (AI) tools to support parts of the hiring process, such as reviewing applications, analyzing resumes, or assessing responses. These tools assist our recruitment team but do not replace human judgment. Final hiring decisions are ultimately made by humans. If you would like more information about how your data is processed, please contact us.

  Read Less

  Apply Now

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