Company Detail

OSI Engineering
Member Since,
Login to View contact details
Login

About Company

Job Openings

  • Cellular 5G/LTE Field & Lab Test Engineer - Product Field Testing of S... Read More
    Cellular 5G/LTE Field & Lab Test Engineer - Product Field Testing of Smartphones/Devices Responsibilities: You will be driven to local and non-local in short notice to test Cellular connectivity of nex-gen smartphones and devices (4 days in the field, 1 day in the lab per work week) You will travel to testing locations up to 1 hour away for the entire day, up to 4 days out of the week. Transportation/Driver will be provided. You will communicate if there is a technical issue and have strong fundamental skills and judgement skills You will judge the testing/data and should be able to move forward without asking for help and be able to adapt quickly Strong analytical skills/good at identifying problems (should be able to judge testing conditions/if testing is going well and how to move forward with the next step instead of constantly calling for help) Able to report back with data, describe technical problems and are easily adaptable Requirements: 1-5 years of cellular testing experience 5G/LTE Stack (Field and Lab) Strong cellular domain understanding in 5GNR and LTE protocol stack Experience with Data, Voice Calls, and/or VoIP testing Testing signal quality and signal integrity on multiple devices Excellent cellular baseband Log analysis is required along with strong troubleshooting Experience troubleshooting common technical setup issues in the field Ability to look at cellular log for on-field debugging Good analytical skills and judgement while executing test campaigns Excellent written and verbal communication skills Must be detail oriented and focused on problem identification Able to travel local and non-local in short notice Recent field-testing experience highly preferred Locations: San Diego, CA (onsite) Duration: 10 months (possible extension) Pay Range: $50-$60/Hr (DOE) Submit resume to Read Less
  • Senior Analog Designer  

    - Agoura Hills
    A leading chip and silicon IP company is seeking a talented Senior Ana... Read More
    A leading chip and silicon IP company is seeking a talented Senior Analog IC Design Engineer to join its Bufferchip Design team in Agoura Hills, California. This is an exciting opportunity to work alongside some of the brightest minds in the industry on innovative products that enhance data speed and security. In this full-time role, the Senior Analog IC Design Engineer will report to the Senior Director of Engineering and play a key role in product definition and design. The position offers high visibility and cross-site collaboration across engineering teams. Responsibilities • Ownership of Analog designs at chip and/or block level • Define optimal architectures to achieve competitive product specifications • Design, simulate and characterize high-performance and high-speed circuits (e.g. Transmitter, Receiver, ADC, DAC, LDO, PLL, DLL, PI circuits). • Create high level model for design tradeoff analysis and behavior model for verification simulations • Create floorplan and work with layout team to demonstrate post extraction performance • Document analysis and simulation to show that design achieves critical electrical, timing parameters and pre-silicon verification flow • Work with the Lab/System team for test plan, silicon bring up and characterization • Understand and disseminate applicable standards and its relevance in a given project to the team • Mentor junior designers Qualifications • MS EE and 5+ years or PhD EE and 2+ years' experience of CMOS analog circuit design. Position may be tailored appropriately with different level of experience. • Prior experience in at least one of the following circuits: Transmitter, Receiver (with CTLE, DFE), PLL, DLL, PI, clock distribution • Good knowledge of design principles for practical design tradeoffs • Fundamental knowledge of basic building blocks like bias, op-amp and LDO • Experience in designing memory interfaces such as DDR 4/5 or serial links such as PCIE is highly desirable • Prior design experience in FinFET process and digitally assisted design is desirable • Experience in modeling with matlab, Verilog-A, verilog is desirable • Experience working in leading R&D and future technology development projects is desirable • The position requires good written & verbal communication skills as well a strong commitment and ability to work in cross functional and globally dispersed teams Location: Agoura Hills, CA (Hybrid) Type: Fulltime Salary Range: $166,000-196,000 (DOE) Read Less
  • Class A Surface Modeler (Alias, NURBs)  

    - Torrance
    We are seeking a highly skilled and detail-oriented Alias Digital Mode... Read More
    We are seeking a highly skilled and detail-oriented Alias Digital Modeler to join a forward-thinking automotive design team that is accelerating its transition from traditional physical modeling to fully digital workflows. This role plays a key part in bridging conceptual design with production-ready digital surfaces, supporting both interior and exterior automotive development. As part of a fast-paced, collaborative studio environment, you'll work alongside designers, engineers, and leadership to develop high-quality interior and exterior surfaces. This role is ideal for modelers with a keen eye for detail, a deep understanding of automotive surfacing principles, and a strong foundation in NURBS and Sub-D modeling. This position is 100% onsite, with no remote or hybrid flexibility. Key Responsibilities: • Convert early concept models (e.g., from Blender or polygonal data) into high-quality NURBS surfaces using Alias. • Build production-level surfaces with refined detail, clean transitions, and manufacturability in mind. • Collaborate closely with designers and engineers to iterate and refine surface models across both interior and exterior components. • Focus on small surface transitions, fillet quality, and precision detailing that elevate the sophistication of the final design. • Support visualization by ensuring models are optimized for rendering in VRED and other real-time tools. • Communicate technical rationale and design feedback effectively across multidisciplinary teams. • Work autonomously and efficiently in a high-pressure, iterative development cycle with tight deadlines. Required Skills & Qualifications: • Open to All Experience Levels, from 2+ years and above: We welcome applicants of varying levels of experience-from junior modelers with strong technical skills and a hunger to grow, to seasoned professionals who bring deep industry expertise. • 3-5+ years of professional experience in automotive 3D surfacing. (Strong junior candidates with exceptional skill will be considered.) • Expertise in Autodesk Alias with advanced Class-A surfacing capabilities. • Strong understanding of NURBS modeling, Sub-D, and surface continuity. • Proven experience detailing fillets and transitional surfaces beyond basic geometry. • Proficiency in VRED for visualization and familiarity with rendering pipelines. • Experience working on both interior and exterior vehicle components. • Prior automotive experience is a must - Work in a design studio at an OEM or automotive supplier will be considered • Ability to work from polygonal data or rough concept models and translate them into clean, refined Alias geometry. • Knowledge of automotive design standards, manufacturing constraints, and form language. • Exposure to real-time rendering tools or knowledge of visualization workflows. • Strong communication skills and ability to collaborate across cross-functional teams and stakeholders. • Ability to adapt quickly, work independently, and deliver high-quality work in a deadline-driven environment. Preferred Qualifications: • Hands-on experience with Blender or similar tools in a digital design workflow. • Strong VIZ skillset with a deep understanding of photo-realistic visualization principles and how they apply to 3D modeling. Type: Contract (12 months to start with possibility of 12-month extension) Location: Torrance, CA Schedule: 5 days onsite required Pay Range: $40/hr-$85/hr (DOE) • This position is open to candidates across a wide range of experience levels, from junior to senior. The anticipated pay range is dependent on years of experience, demonstrated expertise in Alias modeling and surfacing, skillset, and any applicable portfolio quality. Read Less
  • Electrical Component Technician  

    - San Diego
    Electrical Component Technician to support Materials Lab in San Diego... Read More
    Electrical Component Technician to support Materials Lab in San Diego 2+ years' experience with Installation, commissioning, calibration, operating procedure, experimental design, fixture design, equipment operation, results, reporting, documentation Recent and direct experience working with polymers, characterization, dielectric materials, and S parameters. Data analysis and troubleshooting any of the listed machines work on material characterization, data analysis, and share data with the team Lab focused on PCB, FPC, Components, Circuit boards (material wise and process wise) Ensure Lab has full capability and capacity Fill the gap and assist engineers with new systems installed in lab Must be willing to work afternoon shifts (ex: 2pm-8pm) This role may require weekend shifts Type: Contract Duration: 6+ Months Location: San Diego, CA Pay Rate: $55-$70 (DOE) Read Less
  • Technical Incident Manager (TPM)  

    - Cupertino
    Summary: This role focuses on technical incident management for embedd... Read More
    Summary: This role focuses on technical incident management for embedded systems support. The ideal candidate will triage and manage issues across firmware and device driver platforms, working closely with cross-functional teams to investigate, diagnose, and route complex technical incidents. Key Responsibilities: Incident Management: Triage and manage issues across embedded systems and firmware Analyze logs, crash reports, and code to identify root causes Route issues to the appropriate cross-functional teams Track incidents from discovery to resolution Technical Investigation: Debug embedded systems, firmware, and device drivers Read and analyze Python, C, and C++ code Write basic scripts to collect and analyze data Identify recurring technical problems through log and pattern analysis Take full ownership of issues from start to resolution, including monitoring progress, tracking status, and regularly updating stakeholders. Cross-Functional Collaboration: Work closely with Hardware, Software, OS, Test, and Ops teams Communicate findings clearly to technical and non-technical stakeholders Support testing strategies for new product development Qualifications: 5-20 years of experience in embedded systems Strong knowledge of firmware and device driver technologies Skilled in debugging and reading Python, C, and C++ Solid understanding of system logs and crash diagnostics Strong organizational and communication skills Bonus: Experience with data analysis Location: Cupertino, CA (Hybrid; Tues-Thurs onsite) Duration: 6-12+ months Pay Rate Range: $80-$90/hr Read Less
  • SPE Signal Integrity Engineer  

    - San Jose
    SPE Signal Integrity Engineer A leading chip and silicon IP provider i... Read More
    SPE Signal Integrity Engineer A leading chip and silicon IP provider is looking to hire an outstanding Senior Principal Engineer with strong expertise in signal integrity and package design to join the Memory Interface Chips Business Unit engineering team in either San Jose, California or Johns Creek, Georgia. This is a unique opportunity to work alongside some of the brightest engineers and inventors in the world, developing cutting-edge products that help move and protect data faster and more securely. In this full-time and highly visible role, you'll report directly to the VP of Engineering and work within the SI/PI team. You will be responsible for modeling, analysis, and simulation of signal and power integrity for high-performance DDR technologies - operating at speeds of 12800+ MT/s. Responsibilities: Create SI/PI methodologies and work with the Design and SI teams to do SI/PI study and package design for the latest DDR product portfolio Work with our design team and validation team to define specifications and system design requirements such as packaging and PCB routings, IC-PKG-BRD decoupling requirements, channel simulations and jitter sensitivity analysis Provide guideline to design team based on SI/PI study and simulation and silicon correlation so that our products will have superior SI performance, i.e. best RMT scores Work with our customers to do collaboration to find the optimum SI/PI solution Help the team during debug and bring up in lab if needed Requirements: Solid background in SI/PI and package design to provide technical leadership to the team Strong interpersonal skill to keep the team motivated and focused MS or PhD in Electrical Engineering with 10+ years of industry experience in which at least a few years with exposure to DDR4/5 Prior experience in simulating high speed memory (DDR4, DDR5) and/or SERDES interfaces is required Solid theoretical background and understanding in EM and transmission line theory is a must Strong background and solid understanding of equalization techniques such as FIR/FFE/DFE/CTLE are required Must understand package and PCB design, be able to edit APD/Allegro layout files. Know SI/PI driven BGA assignment methodology and be able to simulate for the trade-offs in the context of a system Extensive experience in correlating simulation results with lab measurements using scopes, TDRs, VNAs etc. Strong understanding of the server system, from CPUs to DRAMs on DIMM modules, is highly desirable Know the mechanisms of crosstalk and jitter in source-synchronous interfaces and be able to include the effect of such losses into low BER simulations Proficient with simulations using Spice and ADS Experience with commercial EDA tools such as ADS, HFSS, Q3D/PowerSI Familiarity with RedHawk/Totem or XcitePI and Virtuoso is a strong plus Lab characterization experience of passive components, link margin, or noise using real time/sampling scopes and VNA/TDR is a big plus Basic knowledge of circuits used in high-speed link design is preferred. Excellent writing and presentation skills are essential as well as good communication skills to work with customers and cross-functional teams. Must be an innovative, self-motivated individual, be able to manage and drive his projects, and must be a team player Type: Fulltime and Hybrid work schedule Location: San Jose, CA or Johns Creek, GA Salary Range: $180K-230K (DOE) Read Less
  • PCB Interconnect Characterization and Modeling Specialist We are seeki... Read More
    PCB Interconnect Characterization and Modeling Specialist We are seeking a highly experienced PCB Interconnect Characterization and Modeling Specialist to join our team. The ideal candidate will have a strong background in correlating PCB interconnect measurements with equivalent simulation models in the frequency domain. This position requires expert-level proficiency with de-embedding software such as AFR (Keysight PLTS) and ISD to effectively remove fixture artifacts from measurements. In addition, the candidate must demonstrate expertise in designing 2XTHRU structures specifically for de-embedding purposes. Key Responsibilities: • Perform PCB interconnect simulations with the goal of correlating simulation results with measurements. • De-embedding PCB interconnect fixture artifacts from interconnect lab measurements. • Build and Simulate PCB interconnect models using Ansys HFSS, CST and other simulation tools. Qualifications: • Master's degree in Electrical Engineering or a related field. • Extensive industry experience in PCB interconnect characterization/measurements. • Strong analytical skills and attention to detail. • Excellent communication and documentation skills. • Ability to work independently and as part of a team. Preferred Skills: • Phd in Electrical Engineering. • Experience with data analysis software. • Familiarity with industry standards and best practices. Type: Contract Duration: 6+ Months Location: Cupertino, CA Pay Rate: $110-125/HR (DOE) Read Less
  • Cellular Test Engineer (5GNR/LTE) - Product Field Testing of Smartphon... Read More
    Cellular Test Engineer (5GNR/LTE) - Product Field Testing of Smartphones/Devices Responsibilities: You will be driven to local and non-local in short notice to test Cellular connectivity of nex-gen smartphones and devices (4 days in the field, 1 day in the lab per work week) You will travel to testing locations up to 1 hour away for the entire day, up to 4 days out of the week. Transportation/Driver will be provided. You will communicate if there is a technical issue and have strong fundamental skills and judgement skills You will judge the testing/data and should be able to move forward without asking for help and be able to adapt quickly Not necessarily looking for experts, but candidates with 1-5 years' experience with developed fundamental skills Strong analytical skills/good at identifying problems (should be able to judge testing conditions/if testing is going well and how to move forward with the next step instead of constantly calling for help) Able to report back with data, describe technical problems and are easily adaptable If the candidate is not an expert, you will get trained as long as you have fundamental Requirements: 2-7 years of experience in cellular field testing or cellular QA testing Recent experience directly testing the cellular protocol stack on devices (5G/LTE) Excellent cellular domain wireless, 5GNR and LTE protocol stack Experience troubleshooting common technical setup issues in the field Cellular baseband Log analysis is required with limited to good hands-on experience Experience looking at cellular log for on-field debugging Good analytical skills and judgement while executing test campaigns Ability to quickly adapt and learn Excellent written and verbal communication skills Must be detail oriented and focused on problem identification Able to travel local and non-local in short notice Locations: Cupertino CA (onsite) Duration: 12+ months Pay Range: $50-$60/h (DOE) Read Less
  • CVC/VC Investment Analyst (West Coast)  

    - Mountain View
    Join a globally recognized, innovative automotive company as a CVC/VC... Read More
    Join a globally recognized, innovative automotive company as a CVC/VC Analyst in the West Coast region. You'll help identify and invest in startups aligned with the company's goals of carbon neutrality, advanced mobility, and future ecosystems. This role suits junior professionals with 2-4 years in VC or CVC, particularly those experienced in sourcing and closing deals, and eager to grow in a technically driven environment. Key Responsibilities Strategic Investment ( 70%) Source, identify, and lead investment opportunities independently. Collaborate with Japan-based technical units on startup relevance. Manage end-to-end investment lifecycle and post-investment involvement. Support collaborations even when deals don't proceed. Network Expansion & Ecosystem Engagement ( 30%) Build a strong VC/CVC network and enhance West Coast brand visibility. Lead internal investment processes and pitch high-quality opportunities. Act as point of contact for portfolio companies and internal collaborations. Attend 5-10 ecosystem events/quarter and actively engage in 2+, and represent the company at key events, panels, and startup programs. Required Skillset 2-4+ years' experience in CVC or VC, with direct deal sourcing and execution. Deep-tech investment experience required. Bachelor's in a technical field (Engineering, Chemistry, Physics, etc.). Experience pairing startups with business units or in corporate innovation. Familiar with sectors like Mobility, Energy, Climate Tech, Robotics, AI, etc. Strong technical ramp-up ability, communication, and organizational skills. Comfortable with cross-cultural work, especially with Japan-based teams. Bonus Skills Background in corporate open innovation and startup sourcing. Familiarity with Japanese business culture. Master's or MBA a plus. Experience using PitchBook, Crunchbase, or ecosystem tools. Read Less

Company Detail

  • Is Email Verified
    No
  • Total Employees
  • Established In
  • Current jobs

Google Map

For Jobseekers
For Employers
Contact Us
Astrid-Lindgren-Weg 12 38229 Salzgitter Germany