About Etched
Etched is building AI chips that are hard-coded for individual model architectures. Our first product (Sohu) only supports transformers, but has an order of magnitude more throughput and lower latency than a B200. With Etched ASICs, you can build products that would be impossible with GPUs, like real-time video generation models and extremely deep & parallel chain-of-thought reasoning agents.
Key responsibilities
Support porting state-of-the-art models to our architecture. Help build programming abstractions and testing capabilities to rapidly iterate on model porting.
Build, enhance, and scale Sohu’s runtime, including multi-node inference, intra-node execution, state management, and robust error handling.
Optimize routing and communication layers using Sohu’s collectives.
Utilize performance profiling and debugging tools to identify bottlenecks and correctness issues.
You may be a good fit if you have
Proficiency in C++ or Rust.
Understanding of performance-sensitive or complex distributed software systems like Linux internals, accelerator architectures (e.g. GPUs, TPUs), Compilers, or high-speed interconnects (e.g. NVLink, InfiniBand).
Familiarity with PyTorch or JAX.
Ported applications to non-standard accelerator hardware or hardware platforms.
Strong candidates may have some experience with:
Developed low-latency, high-performance applications using both kernel-level and user-space networking stacks.
Deep understanding of distributed systems concepts, algorithms, and challenges, including consensus protocols, consistency models, and communication patterns.
Solid grasp of Transformer architectures, particularly Mixture-of-Experts (MoE).
Built applications with extensive SIMD (Single Instruction, Multiple Data) optimizations for performance-critical paths.
Benefits
Generous medical, dental, and vision coverage
Housing subsidy of $2,000/month for those living within walking distance of the office
Daily lunch and dinner in our office (plus Grubhub credits)
Relocation support for those who are moving
How we’re different
Etched believes in the Bitter Lesson. We think most of the progress in the AI field has come from using more FLOPs to train and run models, and the best way to get more FLOPs is to build model-specific hardware. Larger and larger training runs encourage companies to consolidate around fewer model architectures, which creates a market for single-model ASICs.
We are a fully in-person team in San Jose and Taipei, and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both as needed.
Compensation Range: $200K - $300K
Read LessAbout Etched
Etched is building the world’s first AI inference system purpose-built for transformers - delivering over 10x higher performance and dramatically lower cost and latency than a B200. With Etched ASICs, you can build products that would be impossible with GPUs, like real-time video generation models and extremely deep & parallel chain-of-thought reasoning agents. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history.
Job Summary
We are seeking highly motivated and detail-oriented software engineers to join our chip simulation team. We’re building Sohu, the world’s first transformer ASIC that leverages tight hardware-software co-design to deliver world-best performance. The chip simulation team plays a key role in hardware-software co-design, enabling early development of the full Sohu software stack. As a software engineer on this team, you will design, develop, and test simulations of our custom hardware systems. You will be working at the cutting edge of hardware innovation, ensuring that our software and hardware teams are able to closely coordinate on their development paths.
Key responsibilities
Simulation Development: Design, develop, and maintain simulations of our hardware. Ensuring high levels of accuracy, efficient debugging, and optimal performance.
Documentation: Create and maintain test plans, work with hardware teams to validate their documentation.
Debug tooling: Build tools to debug simulations, and enable developers to debug software running on the simulator.
Cross-functional Collaboration and Troubleshooting: Chip simulation engineers are expected to work closely with both hardware and software engineers to make sure that our simulations are accurate, and that software engineers are able to use them with a high level of productivity.
You may be a good fit if you have
Proficiency in C/C++
Strong understanding of low-level software engineering.
Strong understanding of hardware engineering.
Excellent communication and collaboration skills.
Strong candidates may also have
Experience developing hardware or system simulations (e.g., SystemC, gem5, QEMU, or custom frameworks).
Experience with custom ML hardware accelerators (e.g., Google TPU)
Experience with firmware, kernel and driver development (e.g., Linux, FreeRTOS)
Experience with hardware development and verification.
Experience with multiprocessing and multithreading.
Familiarity with bit-accurate numerics modeling.
Experience with performance profiling and optimization of simulation code
Proficiency with Python for test harness development, bazel, and git.
Representative projects
Implement a simulation of Sohu’s on-chip modules.
Integrate simulated chips with simulated hosts (QEMU), enabling Kernel driver development and host software testing.
Integrate multiple simulated chips to validate multi-chip software scale-out and scale-up approaches.
Work closely with Sohu software teams in debugging early software deliverables.
Benefits
Full medical, dental, and vision packages, with generous premium coverage
Housing subsidy of $2,000/month for those living within walking distance of the office
Daily lunch and dinner in our office
Relocation support for those moving to San Jose (Santana Row)
Base Salary Compensation
$200,000 - $250,000
How we’re different
Etched believes in the Bitter Lesson. We think most of the progress in the AI field has come from using more FLOPs to train and run models, and the best way to get more FLOPs is to build model-specific hardware. Larger and larger training runs encourage companies to consolidate around fewer model architectures, which creates a market for single-model ASICs.
We are a fully in-person team in San Jose (Santana Row), and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both as needed.
Compensation Range: $200K - $250K
Read LessAbout Etched
Etched is building the world’s first AI inference system purpose-built for transformers - delivering over 10x higher performance and dramatically lower cost and latency than a B200. With Etched ASICs, you can build products that would be impossible with GPUs, like real-time video generation models and extremely deep & parallel chain-of-thought reasoning agents. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history.
Job Summary
We are seeking a talented Computer Architect to join our architecture team and contribute to the design of next-generation AI accelerators. This role focuses on developing and optimizing compute architectures that deliver exceptional performance and efficiency for transformer workloads. You will work on cutting-edge architectural problems and performance modeling with deep cross-functional collaboration to bring innovative chip designs from concept to silicon.
Key Responsibilities
Microarchitecture & dataflow innovation: Design and analyze chip architectures optimized for AI/ML workloads, with focus on throughput, latency, and power efficiency
Design next-generation silicon: Contribute to power and area estimation methodologies for early-stage, next generation architectural exploration
Custom circuit development: Create architectural specifications and interface definitions for compute blocks and subsystems
System‑level prototyping: Collaborate with RTL, verification, physical design, and software teams to ensure architectural feasibility and ultimate optimization
Performance optimization: Conduct architectural experiments using cycle-accurate simulators and analytical models
Cross‑functional collaboration: Support integration efforts by providing architectural guidance and resolving design challenges
You may be a good fit if you have
PhD in Computer Science, Electrical Engineering, Computer Engineering, or related field
5+ years of experience in computer architecture, ASIC design, or related fields
Strong understanding of computer architecture fundamentals including pipelines, memory hierarchies, and interconnects
Experience with performance modeling and architectural simulation tools
Hands‑on experience designing and optimizing floating‑point datapaths or arithmetic‑intensive circuits and working with advanced process nodes.
Proficiency in Rust, C/C++, or Python for modeling and analysis
Knowledge of modern processor microarchitecture and design tradeoffs
Strong analytical and problem-solving skills with attention to detail
Excellent communication skills and ability to work in cross-functional teams
Strong candidates may also have experience with
AI/ML accelerator architectures and dataflow optimization
RTL design and verification (Verilog/SystemVerilog)
Cycle-accurate simulation tools (gem5, SystemC, or custom simulators)
Power and performance analysis methodologies
ASIC design flow and physical design constraints
Publishing or presenting at architecture conferences (ISCA, MICRO, HPCA, etc.)
Hands-on experience with tapeout and silicon bring-up
Benefits
Full medical, dental, and vision packages, with generous premium coverage
Housing subsidy of $2,000/month for those living within walking distance of the office
Daily lunch and dinner in our office
Relocation support for those moving to San Jose (Santana Row)
Base Compensation Range
$200,000 - $265,000
How we’re different
Etched believes in the Bitter Lesson. We think most of the progress in the AI field has come from using more FLOPs to train and run models, and the best way to get more FLOPs is to build model-specific hardware. Larger and larger training runs encourage companies to consolidate around fewer model architectures, which creates a market for single-model ASICs.
We are a fully in-person team in San Jose (Santana Row), and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both as needed.
Read LessAbout Etched
Etched is building the world’s first AI inference system purpose-built for transformers - delivering over 10x higher performance and dramatically lower cost and latency than a B200. With Etched ASICs, you can build products that would be impossible with GPUs, like real-time video generation models and extremely deep & parallel chain-of-thought reasoning agents. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history.
Job Summary
Sohu pushes the boundaries of what’s possible in AI model performance. But Sohu is just our first product - we are looking for talented software engineers to help us build the software, systems, and infrastructure that let us build specialized ASICs faster than any other company on Earth.
This is a broad role. We are looking for hungry, talented software engineers who can contribute to many parts of the systems that make Etched run. You’ll lead the charge in designing and scaling the distributed systems that power our development and deployment pipelines. This is an opportunity to invent high-performance systems that orchestrate fleets of machines across hybrid superclusters, simulate trillions of operations, and move code from idea to silicon faster than ever before.
While this role will work closely with infrastructure (part of the job will be setting up physical supercomputing systems), candidates for this position do not necessarily need infrastructure engineering experience. If you’re obsessed with building robust software for developers to use, designing systems that harness massive compute, and solving problems most companies never encounter, we’d love to talk.
What you’ll do
Build Reliable, High-Performance Systems for Engineering at Scale: Design the core frameworks and workflows that enable Etched’s engineers to iterate faster than anyone else in hardware. This includes building software that drives hybrid superclusters, with an extremely high compute-to-engineer ratio – your work will orchestrate thousands of machines to simulate, verify, and build chips continuously, with performance and correctness guaranteed.
Engineer World-Class Continuous Integration for Hardware: Invent and implement fault-tolerant, high-throughput CI pipelines for our entire backend – simulation, synthesis, CDC, and more. You’ll help build systems that surface correctness and performance regressions across nightly flows, and make high-assurance silicon development as continuous and automated as software deployment.
Scale Bare-Metal Superclusters and Hybrid Infrastructure: Work hands-on with on-prem systems to design compute infrastructure purpose-built for AI chip development. You’ll be orchestrating physical clusters across racks and clouds, thinking deeply about CPU/memory topology, EDA workloads, and how to saturate every core, all the time.
Design High-Quality Tools That Engineers Love Using: EDA workflows are stuck in the early 2000s – non-reproducible, slow, and hard to use. You’ll build from first principles: new interfaces, new dev workflows, and new execution engines that treat compute as cheap and time as sacred. Your tools will turn hours into minutes for the rest of our team.
Representative projects
Tools for Everything: Build a fully automated, correctness-first CI system that continuously runs performance regressions, CDC checks, simulations, and synthesis flows. Make chip verification as fast and seamless as shipping web code.
Massively Parallel Workload Scheduler: Design and deploy a dynamic scheduler for orchestrating compute-heavy workloads across thousands of on-prem and cloud cores. It should balance throughput, reliability, and fault tolerance while abstracting the underlying hardware complexity from users.
On-Demand, GPU-Backed Dev Environments: Create infrastructure that launches reproducible, zero-downtime interactive environments – backed by GPU nodes and hardened against flaky hardware. Developers should be able to spin up environments instantly, run massive workloads, and never worry about cluster volatility.
Scale-Aware Workload Migration: Prototype systems that intelligently migrate CI and simulation workloads across heterogeneous infrastructure, optimizing for performance and minimizing downtime—especially under variable hardware availability and cost constraints.
High-Fidelity Fault Simulation: Develop fault injection and synthetic testing frameworks that simulate hardware failures, degraded networking, and extreme load conditions – validating that our pipelines remain reliable under real-world stress.
You may be a good fit if you
Have Strong Systems Programming Skills: You’re fluent in languages like Go, Rust, or C++ and have familiarity with scripting as well.
Embrace Deep Technical Challenges: You’re not afraid to dive into kernel internals, debug tricky hardware-software interactions, or design low-latency pipelines from first principles.
Are Obsessed With Developer Productivity: You want to build tools that help great engineers move faster and with greater confidence.
Treat Infrastructure as Code: You believe great infrastructure is software – clean, testable, versioned, and designed for maintainability.
Strong candidates may also have experience with
Designing and operating large-scale CI systems, build farms, or simulation clusters.
Architecting hybrid infrastructure across bare-metal and cloud providers.
Optimizing compute environments for performance-critical workloads, including memory-bound simulations and multi-node orchestration.
Working in environments where correctness, reproducibility, and performance are existential requirements.
Benefits
Full medical, dental, and vision packages, with generous premium coverage
Housing subsidy of $2,000/month for those living within walking distance of the office
Daily lunch and dinner in our office
Relocation support for those moving to San Jose (Santana Row)
Base Compensation Range
$150,000 - $275,000
How we’re different
Etched believes in the Bitter Lesson. We think most of the progress in the AI field has come from using more FLOPs to train and run models, and the best way to get more FLOPs is to build model-specific hardware. Larger and larger training runs encourage companies to consolidate around fewer model architectures, which creates a market for single-model ASICs.
We are a fully in-person team in San Jose (Santana Row), and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both as needed.
Read LessAbout Etched
Etched is building the world’s first AI inference system purpose-built for transformers - delivering over 10x higher performance and dramatically lower cost and latency than a B200. With Etched ASICs, you can build products that would be impossible with GPUs, like real-time video generation models and extremely deep & parallel chain-of-thought reasoning agents. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history.
Job Summary
As Etched prepares to scale up customer deployments, we are seeking technical, product-focused members of the team who will bridge the gap between engineering and the go-to-market team. You will lead the design and implementation of our developer portal, which is the primary user-facing touchpoint for customers looking to deploy Sohu servers or developers looking to run their models on Sohu. This is a hands-on technical role that requires expertise in full-stack engineering, and you will collaborate cross-functionally with the software, go-to-market, and platform teams to architect the full customer interface to Sohu.
Key responsibilities
Work with the Etched software team to define and document each layer of the Sohu software stack, from on-chip transaction execution to multi-rack workload sharding and management
Implement live code execution within developer-facing materials
Collaborate with designers to build performant and beautiful UI/UX for developers
Connect interactive documentation with real production hardware to allow users to try out software workloads within sandboxed environments
Curate and present demos of the emulation platform to customers; interface with customers to make and recommend use cases to engineering teams
Work with the go-to-market team to uncover customer requirements and position Sohu capabilities to answer and inform customer questions
Lead the design and implementation of the developer portal as the primary user-facing touchpoint for customers and developers
Collaborate cross-functionally with software, go-to-market, and platform teams to architect the full customer interface to Sohu
You may be a good fit if you have
Bachelor's degree or equivalent practical experience
5+ years of experience in software engineering, with a strong emphasis on full-stack development and systems design
Demonstrated ability to build complex user-facing products with elegant UI/UX and a strong sense of developer ergonomics
Proficiency with modern web frameworks (e.g., React, Next.js, or similar) and backend infrastructure (e.g., Python, Node.js)
Familiarity with inference serving stacks (vLLM, SGLang), ML frameworks (e.g., PyTorch, TensorFlow), and AI hardware acceleration (e.g., CUDA, ROCm, other GPGPU paradigms)
Technical depth: Deeply understands (or can quickly learn) how AI computing infrastructure works from an application layer, software stack, ML research, and data center perspective
Proactive self-starter: Can work across teams to assemble materials, gather data, run meetings, and more with minimal assistance
Opinionated: Spots problems, speaks up when disagreeing, takes ownership, and can handle making important decisions
Strong candidates may also have experience with
Deploying AI applications and infrastructure in the cloud or with on-prem compute clusters
Building developer platforms, portals, or technical documentation tools
Working with APIs, containerization, CI/CD pipelines, and cloud infrastructure (e.g., Docker, Kubernetes, AWS/GCP)
Infrastructure for distributed computing or datacenter-scale systems
Supporting early-stage product launches, especially technical pre-sales
Benefits
Full medical, dental, and vision packages, with generous premium coverage
Housing subsidy of $2,000/month for those living within walking distance of the office
Daily lunch and dinner in our office
Relocation support for those moving to San Jose (Santana Row)
Compensation
$175,000 - $225,000
How we’re different
Etched believes in the Bitter Lesson. We think most of the progress in the AI field has come from using more FLOPs to train and run models, and the best way to get more FLOPs is to build model-specific hardware. Larger and larger training runs encourage companies to consolidate around fewer model architectures, which creates a market for single-model ASICs.
We are a fully in-person team in San Jose (Santana Row), and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both as needed.
Compensation Range: $175K - $225K
Read LessAbout Etched
Etched is building the world’s first AI inference system purpose-built for transformers - delivering over 10x higher performance and dramatically lower cost and latency than a B200. With Etched ASICs, you can build products that would be impossible with GPUs, like real-time video generation models and extremely deep & parallel chain-of-thought reasoning agents. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history.
Job Summary
Lead the Firmware development team for Etched’s groundbreaking Inference Accelerator ASIC. As Senior Firmware Manager, you will guide a talented team of engineers responsible for the entire firmware stack powering our accelerator, including bootloaders, PCI Express performance, ML kernel optimization, power management and security/attestation. Key responsibilities include attracting and developing world-class firmware talent, guiding the firmware technical strategy and architecture, driving quality execution from silicon bring-up through high-volume production, and collaborating closely with ASIC design, hardware platform, system software, validation, and manufacturing partners to deliver robust, high-performance, and secure firmware predictably.
Key responsibilities
Team Leadership & Talent Development: Lead, manage, and inspire a high-caliber team of firmware engineers.
Team Building: Build and scale a world-class firmware team. Attract, hire, and retain, top-tier engineering talent specializing in embedded systems and firmware.
Technical Strategy & Roadmap: Guide and drive the technical strategy and ASIC firmware development roadmap.
Coach and Mentor: Actively coach and mentor team members, fostering professional growth through challenging assignments, targeted development plans, and continuous feedback. Cultivate a team culture focused on firmware excellence, quality, and results.
Execution & Delivery: Oversee the end-to-end firmware development lifecycle – including requirements definition, design, implementation, unit testing, integration, validation support, and release management. Ensure timely delivery of high-quality firmware releases aligned with hardware and software milestones.
Silicon Bring-Up Leadership: Play a critical role in silicon bring-up activities, providing firmware expertise and leading debugging efforts in close collaboration with hardware and validation teams.
Firmware Validation Collaboration: Partner closely with ASIC validation teams to define firmware test plans, review test results, and ensure comprehensive validation coverage.
Cross-Functional Collaboration: Partner effectively with ASIC design, hardware platform engineering, system software development, validation teams, and external manufacturing partners to address system-level challenges.
Firmware Release Management: Oversee maintenance, version control, and release process for validated firmware builds.
Resource Management: Manage project priorities, deadlines, and resources effectively across multiple concurrent projects and deliverables.
You may be a good fit if you have
Proven experience (5+ years) managing firmware or embedded software engineering teams, with direct experience in developing firmware for complex ASICs, SoCs, FPGAs, or similar hardware.
Demonstrated track record of attracting, developing, mentoring, and retaining firmware/embedded engineering talent, building high-performing, diverse, and motivated teams.
Strong architectural understanding across firmware/embedded areas: C/C++ for embedded systems, RTOS/bare-metal development, bootloaders, Root of Trust, low-level hardware initialization.
Experience with low-level interfaces like I2C, SPI, JTAG.
Experience managing the full firmware development lifecycle (specification, design, implementation, test, release, maintenance).
Track record of successfully delivering complex firmware for new hardware platforms, including active participation in silicon bring-up and debugging.
Excellent leadership, communication, and interpersonal skills with the ability to lead firmware efforts and influence cross-functional teams.
Strong problem-solving and debugging skills applied to complex hardware/firmware interactions, proficiency with tools like logic analyzers, oscilloscopes, and debug probes.
Experience with firmware development best practices, source control (Git), and CI/CD methodologies applied to embedded development.
Strong candidates may also have
Direct experience with firmware development and/or validation for AI/ML accelerators or custom data-center accelerator ASICs.
Experience developing or integrating firmware diagnostics and provisioning tools into high-volume manufacturing environments (factory test, system-level test).
Deep expertise in system security concepts relevant to firmware, threat modeling, secure coding practices, and cryptography implementation.
Experience with on-chip debug infrastructure and tools.
Familiarity with server contract manufacturers (CMs) in APAC and collaborating on manufacturing firmware deployment.
Ideal Background
Current Firmware Development Managers/Directors (or similar titles) from semiconductor, ASIC development, server/storage hardware, or cloud infrastructure companies.
Senior technical firmware leads or architects with demonstrated leadership capabilities, strong mentorship skills, and readiness for a management role.
Managers who have led teams responsible for delivering foundational firmware for complex ASICs/SoCs or hardware systems, including silicon bring-up, feature development, and enabling manufacturing test.
Individuals with a strong track record of building and managing teams focused on firmware development, emphasizing technical excellence, quality, security, and talent development within the embedded systems domain.
Benefits
Full medical, dental, and vision packages, with generous premium coverage
Housing subsidy of $2,000/month for those living within walking distance of the office
Daily lunch and dinner in our office
Relocation support for those moving to West San Jose
Compensation Range
$175,000 - $250,000
How we’re different
Etched believes in the Bitter Lesson. We think most of the progress in the AI field has come from using more FLOPs to train and run models, and the best way to get more FLOPs is to build model-specific hardware. Larger and larger training runs encourage companies to consolidate around fewer model architectures, which creates a market for single-model ASICs.
We are a fully in-person team in West San Jose, and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both as needed.
Read LessAbout Etched
Etched is building the world’s first AI inference system purpose-built for transformers - delivering over 10x higher performance and dramatically lower cost and latency than a B200. With Etched ASICs, you can build products that would be impossible with GPUs, like real-time video generation models and extremely deep & parallel chain-of-thought reasoning agents. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history.
Job Summary
We are seeking a highly motivated and skilled Research Scientist with deep expertise in chip microarchitecture, dataflow-centric design, and interconnect/network-on-chip (NoC) optimization to join our central architecture team. This role focuses on pushing the boundaries of performance, efficiency, and scalability for next-generation compute systems by exploring novel microarchitectural innovations and optimizing data movement across the compute fabric.
You will work on cutting-edge problems in defining the architecture of our core compute engines, optimizing them for best PPA, and collaborating with cross-disciplinary teams to prototype and evaluate new ideas and concepts, and eventually make it to a state-of-the-art chip and system we are building.
Key responsibilities
Drive research and development of next-generation chip microarchitecture with a focus on dataflow-centric and interconnect/NoC optimization.
Prototype and evaluate end-to-end compute systems.
Build performance and power models for our next generation chips.
Collaborate with cross-disciplinary teams to explore architectural innovations that enhance performance, efficiency, and scalability.
Contribute to shaping future computing platforms in AI/ML and cloud infrastructure.
You may be a good fit if you have
A PhD in Computer Science, Computer Engineering, Electrical Engineering, or a related technical field, or equivalent practical experience.
Experience in microarchitecture design and hardware-software co-design.
Proficiency in systems-level programming languages such as C or C++.
A strong research background in computer systems design and architecture.
Expertise in chip microarchitecture, dataflow architectures, and network-on-chip/interconnect systems.
Experience with memory hierarchy design, interconnect topologies, coherence protocols, and scalable compute fabrics.
Strong candidates may also have experience with
Publishing in top-tier venues such as ISCA, MICRO, ASPLOS, HPCA, DAC, and SIGARCH.
Hardware modeling tools such as gem5, RTL simulation, or cycle-accurate simulators, along with performance analysis methodologies.
Systems for machine learning (ML), accelerators, and heterogeneous compute platforms.
Designing and building experimental or production-grade computing systems.
Benefits
Full medical, dental, and vision packages, with generous premium coverage
Housing subsidy of $2,000/month for those living within walking distance of the office
Daily lunch and dinner in our office
Relocation support for those moving to West San Jose
Compensation Range
$150,000 - $275,000
How we’re different
Etched believes in the Bitter Lesson. We think most of the progress in the AI field has come from using more FLOPs to train and run models, and the best way to get more FLOPs is to build model-specific hardware. Larger and larger training runs encourage companies to consolidate around fewer model architectures, which creates a market for single-model ASICs.
We are a fully in-person team in West San Jose, and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both as needed.
Read LessAbout Etched
Etched is building the world’s first AI inference system purpose-built for transformers - delivering over 10x higher performance and dramatically lower cost and latency than a B200. With Etched ASICs, you can build products that would be impossible with GPUs, like real-time video generation models and extremely deep & parallel chain-of-thought reasoning agents. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history.
WHAT YOU’LL DO
Co-Develop cutting-edge software optimized across hardware and software driving the full potential of very large transformer models.
Solve challenging problems across the full stack, from low-level drivers and APIs to high-level applications and frameworks.
Contribute to the development of AI solutions that will revolutionize industries like natural language processing, chain of reasoning automation, generative media.
BASIC QUALIFICATIONS:
Bachelor's degree or equivalent practical experience.
3 years of experience in software development, and with data structures/algorithms.
3 years of experience developing and testing software on launching products.
3 years of experience with firmware design, implementation, and troubleshooting.
3 years of experience with embedded architectures, IO technologies (I2C, SPI, PCIe, DRAM etc.), as well as concepts like scalability, fault tolerance, and consistency.
Preferred qualifications:
Master’s degree Computer Science, or a related technical field.
Experience resolving customer-related issues.
Experience solving ambiguous problems.
Excellent verbal and written communication skills.
Why Etched?
Be part of a dynamic startup that's changing the landscape of AI.
Work on the most advanced AI hardware in the world.
Enjoy a competitive salary and benefits package.
Make a meaningful contribution to the future of technology.
Compensation Range
$150,000 - $275,000
If you're a talented software engineer who's excited to shape the future of AI, we encourage you to apply!
To Apply:
Please visit our website at etched.ai/careers to submit your resume and cover letter.
Location: San Jose (Santana West), California
Read Less
About Etched
Etched is building AI chips that are hard-coded for individual model architectures. Our first product (Sohu) only supports transformers, but has an order of magnitude more throughput and lower latency than a B200. With Etched ASICs, you can build products that would be impossible with GPUs, like real-time video generation models and extremely deep & parallel chain-of-thought reasoning agents.
Key responsibilities
Oversee SoC bring-up on emulation platforms; diagnose and resolve failing SoC/Processor tests.Develop innovative techniques to accelerate pre-silicon validation and software development.Provide support for various emulation environments, utilizing advanced emulation techniques including C/C++ DPI transactors, coverage analysis, and in-circuit emulation for high-speed protocols.Collaborate closely with teams across Design, DV, Silicon Validation, Performance, and Software, and partner with leading emulation vendors to enhance platform capabilities and troubleshoot complex issues.Representative projects
Develop high-performance software to capture debugging signals and create associated tooling to surface valuable insights for users.Implement a hybrid emulation environment using custom DPI-based streaming transactors.Create highly configurable chip-to-chip network models using emulation-efficient primitives.You may be a good fit if you have
Hands-on experience with emulation on platforms such as Palladium, Protium, Veloce, or Zebu, covering design bring-up, build flows, debugging, and performance tuning.Strong experience with C/C++ and Linux system development. Proficiency with SystemVerilog and Verilog, including DPI-based interfaces.Practical experience with scripting languages (i.e., Python) for automation.Strong candidates may also have experience with
Experience working with UVM verification environments.Background in design verification, DFT, and testbench modeling.Familiarity with waveform debug tools such as Verdi or SimVision.Benefits
Full medical, dental, and vision packages, with 100% of premium coveredHousing subsidy of $2,000/month for those living within walking distance of the officeDaily lunch and dinner in our officeRelocation support for those moving to CupertinoHow we're different
Etched believes in the Bitter Lesson. We think most of the progress in the AI field has come from using more FLOPs to train and run models, and the best way to get more FLOPs is to build model-specific hardware. Larger and larger training runs encourage companies to consolidate around fewer model architectures, which creates a market for single-model ASICs.
We are a fully in-person team in Cupertino, and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both as needed.
Read LessAbout Etched
Etched is building AI chips that are hard-coded for individual model architectures. Our first product (Sohu) only supports transformers, but has an order of magnitude more throughput and lower latency than a B200. With Etched ASICs, you can build products that would be impossible with GPUs, like real-time video generation models and extremely deep & parallel chain-of-thought reasoning agents. Etched Labs is the organization within Etched whose mission is to democratize generative AI, pushing the boundaries of what will be possible in a post-Sohu world.
Key responsibilities
Propose and conduct novel research to achieve results on Sohu that are unviable on GPUsTranslate core mathematical operations from the most popular Transformer-based models into maximally performant instruction sequences for SohuDevelop deep architectural knowledge informing best-in-the-world software performance on Sohu HW, collaborating with HW architects and designers.Co-design and finetune emerging model architectures for highest efficiency on SohuGuide and contribute to the Sohu software stack, performance characterization tools, and runtime abstractions by implementing frontier models using Python and Rust.Representative projects
Propose and implement a novel test time compute algorithm that leverages Sohu's unique capabilities to unlock a product could never be achieved on a typical GPUImplement diffusion models on Sohu to achieve GPU-impossible latencies that allow for real-time image generationOptimize model instructions and scheduling algorithms to optimize for utilization, latency, throughput, and/or a mix of these metrics. Implement model-specific inference-time acceleration techniques such as speculative decoding, tree search, KV cache sharing, priority scheduling, etc by interacting with the rest of the inference serving stack.You may be a good fit if you have
An ML Research background with interests in HW co-designExperience with Python, Pytorch, and / or JAXFamiliarity with transformer model architectures and/or inference serving stacks (vLLM, SGLang, etc.) and/or experience working in distributed inference/training environmentsExperience working cross-functionally in diverse software and hardware organizationsStrong candidates may also have
ML Systems Research and HW Co-design backgroundsPublished inference-time compute research and/or efficient ML researchExperience with RustFamiliarity with GPU kernels, the CUDA compilation stack and related tools, or other hardware acceleratorsBenefits
Full medical, dental, and vision packages, with 100% of premium coveredHousing subsidy of $2,000/month for those living within walking distance of the officeDaily lunch and dinner in our officeRelocation support for those moving to CupertinoHow we're different
Etched believes in the Bitter Lesson. We think most of the progress in the AI field has come from using more FLOPs to train and run models, and the best way to get more FLOPs is to build model-specific hardware. Larger and larger training runs encourage companies to consolidate around fewer model architectures, which creates a market for single-model ASICs.
We are a fully in-person team in Cupertino, and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both as needed.
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