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Eliyan
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  • PD - Principal, Physical Design  

    - Mundelein
    Job DescriptionJob DescriptionJoin the leading chiplet startup! As an... Read More
    Job DescriptionJob DescriptionJoin the leading chiplet startup! As an Eliyan Principal Physical Design Engineer, you will be working at a fast-paced early-stage startup creating technologies that fuel tomorrow’s chiplet based systems with best-in-class power, area, manufacturability, and design flexibility. You will drive the development of cutting-edge ASICs from RTL to GDSII.  You will work with a cross-functional team of industry experts that operate from first principles, innovate, and push the envelope to create high-volume and high-performance manufacturable products. In this role, you will oversee and optimize the entire design flow, including synthesis, place-and-route (PnR), static timing analysis (STA), electromigration/IR drop analysis (EM/IR), and physical verification (PV). You will also focus on developing and improving design flows and methodologies to ensure high-quality, on-time delivery. We offer a fun work environment with excellent benefits.Responsibilities:Architecture and packaging driven floorplanning and integration so physical partitions match system and package constraintsWell defined boundaries with lego style pin alignment and consistent interface placement across chip and blocksFeedthrough, repeater and bus planning with early reservation of routing corridors, layers, and resources for cross block connectivity.Define clocking architecture methodology selecting spine and rib, H tree, or mesh to optimize power, skew, latency, and robustness.Establish CTS methodology including skew and latency targets, buffer and ICG strategy, NDR and shielding rules for critical clock routes.Define skew groups and balancing strategy across library corners, ensuring consistent behavior under MMMC variations and derates.Drive clock constraint quality across hierarchy with clean chip to block and block to chip handoff for signoff readiness.Define DRC aware power grid architecture including rings, straps, and mesh, matching metal resistivity assumptions to IR drop targets and EM limits.Ensure careful planning around analog routing with keepouts, shielding, spacing, and grid topology choices that preserve sensitive nets and meet DRC.Drive lego aligned power mesh alignment across top level, subsystem, and block level with consistent strap pitch, via patterns, and clean connectivity.Lead early and signoff EM and IR analysis, identify hotspots, and implement grid reinforcement and via optimization without routing or congestion penalties.Align power planning with floorplan and package constraints including bump map, current demand, and entry points to minimize noise and IR drop.Qualifications:8 to 12 years ASIC physical design experience owning floorplanning integration clocking and power planning from early feasibility through signoff and tapeout on complex SoCsExpert in architecture and package driven hierarchy planning with lego aligned boundaries pin strategy feedthrough repeater bus planning plus CTS methodologies including spine rib H tree or meshStrong EM IR PV and STA awareness with MMMC and library corner skew group balancing advanced node exposure TSMC 3nm 2nm or Samsung 2nm and functional ECO execution experience

    We may use artificial intelligence (AI) tools to support parts of the hiring process, such as reviewing applications, analyzing resumes, or assessing responses. These tools assist our recruitment team but do not replace human judgment. Final hiring decisions are ultimately made by humans. If you would like more information about how your data is processed, please contact us.

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  • Job DescriptionJob DescriptionON-SITE (BAY AREA)Join the leading chipl... Read More
    Job DescriptionJob DescriptionON-SITE (BAY AREA)Join the leading chiplet startup! As an Eliyan Principal Technical Program Manager, you will be working at a fast-paced early-stage startup creating technologies that fuel tomorrow’s chiplet based systems with best-in-class power, area, manufacturability, and design flexibility. You will be responsible for leading, planning, and help execute ASIC development and platform program. You will work with a cross-functional team of experts that operate from first principles, innovate and push the envelope to create high-volume and high-performance manufacturable products. We offer a fun work environment with excellent benefits.Key Responsibilities:Program Leadership: Manage and oversee all phases of ASIC and platform development, including architecture, design, verification, validation, bring-up, and production readiness.Cross-Functional Coordination: Work closely with internal teams, including digital design, design verification, DFT, physical design, analog design, packaging and substrate design, PCB and platform design, silicon bring-up, firmware, and software teams.Vendor and Customer Management: Collaborate with external vendors for IP sourcing, ensuring compliance with project timelines and requirements. Interface with customers to define deliverables and ensure seamless integration of IP and silicon solutions.Schedule and Risk Management: Define program timelines, set milestones, and proactively identify and mitigate risks to ensure timely project delivery.Budget and Resource Allocation: Manage program budgets, allocate resources efficiently, and track expenses to optimize development efforts.Technical Reviews and Decision-Making: Conduct regular program reviews, assess technical challenges, and drive strategic decisions to optimize performance, cost, and schedule.Process Improvement: Define and enhance program management best practices, improving execution efficiency across teams and projects.Documentation and Reporting: Maintain clear and detailed documentation, provide regular program updates, and report progress to key stakeholders.Qualifications:Bachelor’s or Master’s degree in Electrical or Computer Engineering, or a related field.15+ years of experience in semiconductor program management, with a strong background in ASIC development.Proven ability to lead and drive large-scale, complex semiconductor projects across multiple disciplines.Experience in working with external IP vendors and customers on deliverables and integration requirements.Strong understanding of the entire silicon development lifecycle, including front-end and back-end design, packaging, PCB design, and bring-up.Excellent problem-solving, leadership, and decision-making skills.Strong verbal and written communication skills, with the ability to interface with both technical and non-technical stakeholders.Experience with project management tools (e.g., Jira, MS Project, Confluence) and methodologies (Agile, Waterfall).Experience with networking ASICs, mixed-signal PHY SOCs, high-performance computing, AI/ML accelerators preferredKnowledge of firmware and software development in relation to silicon bring-up.PMP or similar program management certification is a plus.

    We may use artificial intelligence (AI) tools to support parts of the hiring process, such as reviewing applications, analyzing resumes, or assessing responses. These tools assist our recruitment team but do not replace human judgment. Final hiring decisions are ultimately made by humans. If you would like more information about how your data is processed, please contact us.

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Astrid-Lindgren-Weg 12 38229 Salzgitter Germany