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  PD - Sr Staff -- CAD & Design Methodology \u007C RTL-to-GDSII Flow \u007C Advanced Node Methodology  

  Eliyan

  full_time - Mundelein

  Posted: 11/05/2026

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  Job DescriptionJob DescriptionABOUT THE ROLEAs a Sr Staff / Principal... Read More

  Job DescriptionJob Description

  ABOUT THE ROLE

  As a Sr Staff / Principal CAD & Design Methodology Engineer, you will be the technical architect of RTL-to-GDSII flows and digital design infrastructure for advanced SoC products. You will define and deploy multi-vendor, multi-foundry design methodology platforms, lead hierarchical SoC implementation strategies, and drive low-power chiplet products. You will own the R2G (RTL-to-GDSII) system architecture spanning Intel, TSMC, Samsung, and GlobalFoundries nodes — enabling scalable, high-quality tapeouts across diverse product classes.

  We may use artificial intelligence (AI) tools to support parts of the hiring process, such as reviewing applications, analyzing resumes, or assessing responses. These tools assist our recruitment team but do not replace human judgment. Final hiring decisions are ultimately made by humans. If you would like more information about how your data is processed, please contact us.

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  Digital - SerDes Digital Design Lead  

  Eliyan

  full_time - Mundelein

  Posted: 20/02/2026

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  Job DescriptionJob DescriptionJoin the leading chiplet startup!  As th... Read More

  Job DescriptionJob DescriptionJoin the leading chiplet startup!  As the SerDes Digital Design Lead at Eliyan, you will drive the architecture and implementation of next-generation high-speed serial link IPs targeting 224G and 448G data rates for chiplet-based systems with best-in-class power, area, manufacturability, and design flexibility.  You will lead the digital design of SerDes transmitter and receiver datapaths, clock and data recovery (CDR) digital logic, equalization engines, and PHY-level controller logic for cutting-edge interconnect products.  You will work with a cross-functional team of experts that operate from first principles, innovate and push the envelope to create high-volume and high-performance manufacturable products.  We offer a fun work environment with excellent benefits.Key Responsibilities:Lead the micro-architecture definition and RTL implementation of high-speed SerDes digital blocks targeting 224G PAM4 and 448G signaling, including DSP-based equalization (FFE, DFE, CTLE digital controls), CDR loop logic, and adaptation enginesDesign and optimize PHY-level digital logic including TX driver control, RX datapath, PCS sublayers, lane alignment, deskew, and gear-boxing/rate-matching logicArchitect and implement forward error correction (FEC) encoder/decoder blocks including RS-FEC (KP4/KP8), interleaving, and low-latency FEC architectures optimized for 224G/448G link budgetsDrive RTL design quality through lint, CDC/RDC analysis, synthesis optimization, and close collaboration with physical design and timing closure teams on advanced FinFET/GAA process nodesCollaborate closely with analog/mixed-signal designers on SerDes AFE integration, digital-to-analog interface specification, calibration sequencing, and AMS co-simulation bring-upOwn design deliverables and milestones from RTL development through tapeout signoff; coordinate with verification, DFT, and backend teams to meet aggressive schedulesDefine and implement auto-negotiation, link training, and PHY initialization state machines compliant with IEEE 802.3Develop power-efficient digital architectures with emphasis on clock gating, voltage scaling, and low-power design techniques for data center and AI/ML interconnect applicationsParticipate in standards bodies and stay current with emerging 224G/448G specifications, OIF CEI, and next-generation interconnect standardsDesign firmware-accessible register interfaces, configuration/calibration logic, and DPI-based firmware co-simulation hooks for PHY bring-up and debugSupport post-silicon characterization and debug activities; correlate silicon measurements with pre-silicon simulation results to drive design improvementsQualifications:Masters or Ph.D in Electrical Engineering, Computer Engineering, or related fields12+ years of experience in digital design of high-speed SerDes, PHY, or transceiver IPs with proven tapeout experience at 112G PAM4 or higher data ratesStrong RTL design skills in SystemVerilog with deep understanding of synthesis, timing closure, CDC/RDC, and design-for-test (DFT) methodologiesExpert-level knowledge of SerDes DSP architectures including FFE, DFE, MLSE, CTLE digital controls, CDR loop dynamics, and adaptation/calibration algorithms for PAM4 signalingStrong working knowledge of IEEE 802.3 (100G/200G/400G/800G/1.6T), OIF CEI specifications, FEC architectures (RS-FEC KP4/KP8), and/or die-to-die standards such as UCIeHands-on experience with high-speed digital design on advanced process nodes (5nm, 3nm, or below) with understanding of FinFET/GAA device implications on circuit performance and powerExperience working at the digital-analog boundary including specification of DAC/ADC interfaces, calibration state machines, and integration with mixed-signal simulation environmentsDemonstrated technical leadership with ability to mentor engineers, drive architectural decisions, and deliver silicon on aggressive schedules in startup or high-growth environmentsExperience with optical/electrical interconnects (VCSEL, EML), chiplet D2D interfaces, DRAM PHYs, or HBM memory interfaces a plus

  We may use artificial intelligence (AI) tools to support parts of the hiring process, such as reviewing applications, analyzing resumes, or assessing responses. These tools assist our recruitment team but do not replace human judgment. Final hiring decisions are ultimately made by humans. If you would like more information about how your data is processed, please contact us.

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  PD - Principal, Physical Design  

  Eliyan

  full_time - Mundelein

  Posted: 09/02/2026

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  Job DescriptionJob DescriptionJoin the leading chiplet startup! As an... Read More

  Job DescriptionJob DescriptionJoin the leading chiplet startup! As an Eliyan Principal Physical Design Engineer, you will be working at a fast-paced early-stage startup creating technologies that fuel tomorrow’s chiplet based systems with best-in-class power, area, manufacturability, and design flexibility. You will drive the development of cutting-edge ASICs from RTL to GDSII.  You will work with a cross-functional team of industry experts that operate from first principles, innovate, and push the envelope to create high-volume and high-performance manufacturable products. In this role, you will oversee and optimize the entire design flow, including synthesis, place-and-route (PnR), static timing analysis (STA), electromigration/IR drop analysis (EM/IR), and physical verification (PV). You will also focus on developing and improving design flows and methodologies to ensure high-quality, on-time delivery. We offer a fun work environment with excellent benefits.Responsibilities:Architecture and packaging driven floorplanning and integration so physical partitions match system and package constraintsWell defined boundaries with lego style pin alignment and consistent interface placement across chip and blocksFeedthrough, repeater and bus planning with early reservation of routing corridors, layers, and resources for cross block connectivity.Define clocking architecture methodology selecting spine and rib, H tree, or mesh to optimize power, skew, latency, and robustness.Establish CTS methodology including skew and latency targets, buffer and ICG strategy, NDR and shielding rules for critical clock routes.Define skew groups and balancing strategy across library corners, ensuring consistent behavior under MMMC variations and derates.Drive clock constraint quality across hierarchy with clean chip to block and block to chip handoff for signoff readiness.Define DRC aware power grid architecture including rings, straps, and mesh, matching metal resistivity assumptions to IR drop targets and EM limits.Ensure careful planning around analog routing with keepouts, shielding, spacing, and grid topology choices that preserve sensitive nets and meet DRC.Drive lego aligned power mesh alignment across top level, subsystem, and block level with consistent strap pitch, via patterns, and clean connectivity.Lead early and signoff EM and IR analysis, identify hotspots, and implement grid reinforcement and via optimization without routing or congestion penalties.Align power planning with floorplan and package constraints including bump map, current demand, and entry points to minimize noise and IR drop.Qualifications:8 to 12 years ASIC physical design experience owning floorplanning integration clocking and power planning from early feasibility through signoff and tapeout on complex SoCsExpert in architecture and package driven hierarchy planning with lego aligned boundaries pin strategy feedthrough repeater bus planning plus CTS methodologies including spine rib H tree or meshStrong EM IR PV and STA awareness with MMMC and library corner skew group balancing advanced node exposure TSMC 3nm 2nm or Samsung 2nm and functional ECO execution experience

  We may use artificial intelligence (AI) tools to support parts of the hiring process, such as reviewing applications, analyzing resumes, or assessing responses. These tools assist our recruitment team but do not replace human judgment. Final hiring decisions are ultimately made by humans. If you would like more information about how your data is processed, please contact us.

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  Package & SI/PI - Senior/Staff Packaging Engineer - Electro-Thermal  

  Eliyan

  full_time - Mundelein

  Posted: 20/10/2025

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  Job DescriptionJob DescriptionJoin the leading chiplet interconnect st... Read More

  Job DescriptionJob DescriptionJoin the leading chiplet interconnect startup! We are seeking an experienced Senior/Staff Packaging Engineer specializing in electro-thermal simulation to join our advanced packaging team. You will develop comprehensive thermal and electrical simulations for next-generation semiconductor packaging solutions, including 2.5D/3D IC integration, chiplet-based systems, and advanced heterogeneous integration technologies. This role is critical in enabling high-performance computing, AI accelerators, and advanced chiplet architectures. We offer a fun work environment with excellent benefits. ONSITE M-FKey Responsibilities: Develop detailed thermal models for 2.5D/3D IC packages, chiplets, and multi-die systems; perform steady-state and transient thermal analysis with hotspot identificationExecute power integrity (PI) and IR drop analysis; optimize power distribution networks (PDN) and power delivery architecturesConduct electromigration (EM) and reliability analysis for interconnects, bumps, TSVs, and redistribution layers (RDL)Develop chip-package co-simulation workflows using industry-standard EDA tools (ANSYS RedHawk\u0002SC, RHSC-ET, SIwave, Cadence Sigrity/Clarity)Create hierarchical compact macro models (CMM) and reduced-order thermal models for early\u0002stage design optimizationAutomate simulation workflows using Python, TCL, and Shell scripting; build design space exploration toolsCollaborate with silicon design, package design, and manufacturing teams on design-for-reliability (DFR) initiativesSupport customer engagements with technical analysis and present findings to stakeholdersMinimum Qualifications: Education:PhD in Electrical/Mechanical Engineering, or related field with focus on thermal management, power delivery, or electronic packaging (Master's with 5+ years experience considered)Strong academic background in power integrity, signal integrity, and thermal management for advanced packaging Technical Skills: Expert proficiency in: ANSYS RedHawk-SC, RHSC Electrothermal, Totem, PathFinder, SIwave, HFSS, Q3D; Cadence Voltus, Sigrity, Clarity; Synopsys RedHawk Fusion, PrimeTime, ICC2Experience with physical design tools (Cadence Innovus, Synopsys ICC2, Siemens Calibre) and RTL\u0002to-GDSII flowsStrong programming/scripting: Python, C/C++, Tcl, Shell (bash); Verilog/VHDL/SystemVerilog for verificationKnowledge of advanced packaging: 2.5D/3D ICs (CoWoS, InFO, EMIB), chiplets, TSVs, interposers, FOWLP, RDL design Domain Expertise:  Deep understanding of EM/IR analysis, power integrity, thermal physics, and electrothermal co\u0002simulationExpertise in heat transfer principles (conduction, convection, radiation), thermal material properties, and CTE mismatchKnowledge of chiplet standards (UCIe and BoW), die-to-die interfaces, and wafer-scale integrationHands-on experience with semiconductor package thermal/electrical analysis and tape-outs Ideal Qualifications:Familiarity with machine learning applications in EDA and design optimizationExperience with HPC, AI/ML accelerator packaging, or co-packaged optics (CPO)Background in reliability testing (thermal cycling, HTOL, THB) and measurement correlationWhat we are looking for:Strong analytical mindset with expertise across multiple physics domains (thermal, electrical, mechanical)Excellent communication skills to present complex technical concepts to diverse audiencesCross-functional collaboration abilities to work with silicon, package, product, and manufacturing teamsSelf-motivated professional who thrives in fast-paced environments with minimal supervisionContinuous learner staying current with emerging technologies; innovation-driven with creative problem-solvingResults-oriented engineer delivering high-quality work to enable product milestones on schedule

  We may use artificial intelligence (AI) tools to support parts of the hiring process, such as reviewing applications, analyzing resumes, or assessing responses. These tools assist our recruitment team but do not replace human judgment. Final hiring decisions are ultimately made by humans. If you would like more information about how your data is processed, please contact us.

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  Program Management - Principal / Sr. Principal Technical Program Manager (Semiconductor)  

  Eliyan

  full_time - Mundelein

  Posted: 16/10/2025

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  Job DescriptionJob DescriptionON-SITE (BAY AREA)Join the leading chipl... Read More

  Job DescriptionJob DescriptionON-SITE (BAY AREA)Join the leading chiplet startup! As an Eliyan Principal Technical Program Manager, you will be working at a fast-paced early-stage startup creating technologies that fuel tomorrow’s chiplet based systems with best-in-class power, area, manufacturability, and design flexibility. You will be responsible for leading, planning, and help execute ASIC development and platform program. You will work with a cross-functional team of experts that operate from first principles, innovate and push the envelope to create high-volume and high-performance manufacturable products. We offer a fun work environment with excellent benefits.Key Responsibilities:Program Leadership: Manage and oversee all phases of ASIC and platform development, including architecture, design, verification, validation, bring-up, and production readiness.Cross-Functional Coordination: Work closely with internal teams, including digital design, design verification, DFT, physical design, analog design, packaging and substrate design, PCB and platform design, silicon bring-up, firmware, and software teams.Vendor and Customer Management: Collaborate with external vendors for IP sourcing, ensuring compliance with project timelines and requirements. Interface with customers to define deliverables and ensure seamless integration of IP and silicon solutions.Schedule and Risk Management: Define program timelines, set milestones, and proactively identify and mitigate risks to ensure timely project delivery.Budget and Resource Allocation: Manage program budgets, allocate resources efficiently, and track expenses to optimize development efforts.Technical Reviews and Decision-Making: Conduct regular program reviews, assess technical challenges, and drive strategic decisions to optimize performance, cost, and schedule.Process Improvement: Define and enhance program management best practices, improving execution efficiency across teams and projects.Documentation and Reporting: Maintain clear and detailed documentation, provide regular program updates, and report progress to key stakeholders.Qualifications:Bachelor’s or Master’s degree in Electrical or Computer Engineering, or a related field.15+ years of experience in semiconductor program management, with a strong background in ASIC development.Proven ability to lead and drive large-scale, complex semiconductor projects across multiple disciplines.Experience in working with external IP vendors and customers on deliverables and integration requirements.Strong understanding of the entire silicon development lifecycle, including front-end and back-end design, packaging, PCB design, and bring-up.Excellent problem-solving, leadership, and decision-making skills.Strong verbal and written communication skills, with the ability to interface with both technical and non-technical stakeholders.Experience with project management tools (e.g., Jira, MS Project, Confluence) and methodologies (Agile, Waterfall).Experience with networking ASICs, mixed-signal PHY SOCs, high-performance computing, AI/ML accelerators preferredKnowledge of firmware and software development in relation to silicon bring-up.PMP or similar program management certification is a plus.

  We may use artificial intelligence (AI) tools to support parts of the hiring process, such as reviewing applications, analyzing resumes, or assessing responses. These tools assist our recruitment team but do not replace human judgment. Final hiring decisions are ultimately made by humans. If you would like more information about how your data is processed, please contact us.

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